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Implementing Serial-to-Parallel Buffering with an Optimized FPGA VI

Last Modified: August 9, 2018

Memory resources might pass array data differently than you want to process it. For example, a DMA FIFO passes array data one element at a time. However, you might design your code to process all the array elements at once. You can use a simple Optimized FPGA VI to collect the array elements from the FIFO so you can process the elements together.

Complete the following steps to implement serial-to-parallel buffering and parallel-to-serial buffering in a top-level FPGA VI using a wire in a simple Optimized FPGA VI:

  1. Create a VI in an Optimized FPGA Library that includes an array control wired to an array indicator, as shown in the following image.
  2. Configure the connector pane of the Optimized FPGA VI so you can call it from a top-level FPGA VI.
  3. From a top-level FPGA VI, place the Optimized FPGA VI in a Clock-Driven Loop. To place the Optimized FPGA VI on the diagram, drag it from the Software category in the Project Items palette. LabVIEW encases the Optimized FPGA VI in an integration node.
  4. To implement parallel-to-serial buffering, configure the Optimized FPGA VI integration node to use standard mode for inputs and element-by-element mode for outputs. To implement serial-to-parallel buffering, configure the Optimized FPGA VI integration node to use element-by-element mode for inputs and standard mode for outputs.


In the following example, the top-level VI reads data serially from the host, reverses the data, and streams the resulting data serially back to the host.
  1. Parallel-to-serial buffering—Uses standard mode for inputs, element-by-element mode for outputs.
  2. Serial-to-parallel buffering—Uses element-by-element mode for inputs, standard mode for outputs.

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