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Transferring Optimized FPGA VIs to Hardware

Last Modified: August 8, 2018

The process of transferring your Optimized FPGA VI to hardware includes setting performance directives for your Optimized FPGA VI, estimating the FPGA resources it requires, and optimizing your design if it does not meet performance requirements. The following flowchart outlines the process. Click the blue rectangles for more information about each step.

nihelp://fpgaip-prog/fpgaip-directives/ nihelp://fpgaip-prog/fpgaip-directives/ nihelp://fpgaip-prog/fpgaip-interface-modes/ nihelp://fpgaip-prog/ensure-fpgaip-fit-fpga/ nihelp://fpgaip-prog/fpgaip-best-practices/ nihelp://fpgaip-prog/adjusting-directives/ nihelp://fpga-targets/compiling-build-spec-fpga/

If your compilation does not succeed, investigate build errors for failed items in the Build Queue tab. Investigating build errors opens the Timing Violations tab, which you can use to determine what part of the design failed to meet timing requirements. If timing failed in the Optimized FPGA VI, adjust the performance directives for the VI. If timing fails elsewhere in the application, debug that part of the application.


Timing issues with Optimized FPGA VIs can sometimes display in the Optimized or Non-Diagram Logic category of the Timing Violations tab.

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