In a Clock-Driven Loop on the diagram of an FPGA VI or in a Clock-Driven Logic (CDL) document, you can check intermediate values and view changes in signal data over time by right-clicking a wire and selecting Set sampling probe. Use the Sampling Probes tab to interact with the data collected from sampling probes.
Consider the following tips and tricks for using sampling probes:
Each sampling probe reports data at each rising edge of the clock that drives the Clock-Driven Loop containing the probe. Aligning the cursor with the edge of the clock signal allows you to view the data values as they change at an interval of one loop iteration. To compare sampling probe data to clock signals in the graph, include the following code on the subdiagram of one Clock-Driven Loop for the clock that drives the code you are testing.