Timing violations occur when the execution time requested by sections of code is shorter than execution time the bitfile achieves after compiling. The compilation for a bitfile must be free of errors before you run the code on the FPGA. After you compile a bitfile for an FPGA target, the Timing Violations tab displays timing violations that occur during compilation.
Resolve timing violations using the following steps.
Each node takes a certain amount of time to execute, so use fewer nodes inside each Clock-Driven Loop by simplifying the logic of the code, if possible. Long node paths inside a Clock-Driven Loop result in timing delays when compiled on the FPGA. Also, avoid deeply nested Case Structures to reduce the length of paths inside a Clock-Driven Loop.
Pipelining is the process of restructuring one long section of code into several shorter sections that run in parallel. Pipelining takes advantage of the parallel processing capabilities of the FPGA to increase efficiency of sequential code.
To implement pipelining, divide code into discrete steps and wire the inputs and outputs of each step to Feedback Nodes in the Clock-Driven Loop. The following image shows code organized into subCDLs and pipelined through Feedback Nodes.
Use the smallest data type possible for terminals to decrease the size and increase the speed of an FPGA VI. For example, if a terminal uses a 32-bit integer data type by default, but you know the terminal will never contain a number above 255, change the data type of the terminal to an 8-bit integer to use fewer FPGA resources.
If your application does not explicitly depend on completing each clock cycle at exactly the rate specified, reduce the frequency of the clock that drives the components that failed to meet timing requirements.
If your failed compilation misses the required throughput time by only a few nanoseconds, try recompiling your bitfile. Each compilation of a bitfile does not always produce identical results on the FPGA, so recompiling sometimes resolves minor timing violations.
If your bitfile continues to return timing violations, repeat the previous strategies. If you cannot eliminate timing violations, consider moving parts of your application to the host processor.
The Timing Violations tab reports errors under Optimized or Non-Diagram Logic whenever LabVIEW cannot determine the location of the timing violation in the compiled code. Timing violations for Clock-Driven Logic code, Multirate Dataflow code, and Optimized FPGA VI code often appear under Optimized or Non-Diagram Logic in the Timing Violations pane.
The compiler often implements common operations (i.e. Add, Multiply) in dedicated resource blocks to optimize the performance of the code. As a result, part of your critical path from a Clock-Driven Logic document or a Clock-Driven Loop often appears under Optimized or Non-Diagram Logic.
On the Document tab, decrease the Clock Rate and increase the Pipelines for the code to improve timing.
On the Document tab, select FPGA Estimates and increase the Routing Margin and Clock Rate to improve the timing in the code. If the Optimized or Non-Diagram Logic object still shows a large delay after you revise the FPGA Estimates configuration, try revising your Optimized FPGA VI algorithm. Verify that the clock rate you requested for your Optimized FPGA VI matches the clock rate of the Clock-Driven Loop or Clock-Driven Logic document that calls the Optimized FPGA VI.