Table Of Contents

Monitoring the Compilation of a Bitfile

Last Modified: August 13, 2018

An FPGA target contains a limited number of resources. If a bitfile requires more resources than the FPGA target has available, the compilation of the bitfile fails. Use the estimated and actual number of resources a bitfile uses to determine changes you need to make to code.

Compilation can take a long time, during which you can monitor the process and cancel a compilation if you encounter severe errors. You do not have to wait for the entire process to finish.

After you begin the process of building a bitfile, complete the following steps to monitor the compilation of the bitfile:

  1. Double-click a bitfile row in the Build Queue tab to monitor the status of your bitfile during compilation.
    spd-note-note
    Note  

    Do not change any code in your FPGA application during the diagram analysis stage of compilation. Any changes you make to code during the diagram analysis stage may be reflected in the bitfile. If you want to continue working on code while you wait for the compilation to finish, do so after the diagram analysis stage.

  2. After the synthesizing stage of compilation, click each resource listed under Estimated resource usage to view the estimated FPGA resources that your bitfile requires. If your bitfile is estimated to need more resources than the FPGA target contains, cancel the compilation and revise your code. After you cancel a compilation, you must begin a new compilation to compile your updated code.
  3. Click the resources listed under Actual resource usage to see the total number of each resource used on the FPGA target. If your compilation fails, you can use the resource usage information to investigate errors or determine changes you need to make in your code. For example, if your bitfile uses all LUTs from the FPGA, but few block RAMs, you may need to change the way you implement memory or FIFOs in your code.

After the compilation is complete, proceed with one of the following tasks:

  • If the Timing Violations tab displays timing violations, fix the timing violations and recompile the bitfile. Refer to Resolving Timing Violations on the FPGA for tips to fix timing violations.
  • If the Timing Violations tab displays no timing violations, you can deploy the bitfile to an FPGA. Refer to Downloading and Running an FPGA VI for help downloading and running the compiled bitfile on an FPGA. When you run the bitfile on an FPGA, the bitfile reconfigures the FPGA circuit of the FPGA by transferring all the code and performance requirements of your application to the FPGA.

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