An FPGA VI is a VI that you target to an FPGA.
Designate a top-level FPGA VI within an Application document (.gcomp) that represents a bitfile. The top-level FPGA VI serves as the container for your overall FPGA application. Place all of the code that makes up your FPGA application either directly on the diagram of the FPGA VI, or within subdocuments located on the diagram of the FPGA VI. This code can include Clock-Driven Logic and Optimized FPGA VIs. You compile the FPGA application to create a bitfile, so any code referenced within the top-level FPGA VI compiles as part of the FPGA application.
Because the resources available to a program running on an FPGA differ from those available on the host, an FPGA VI includes only palette objects and data types that are compatible with an FPGA. For example, the palette in an FPGA VI displays nodes and terminals that receive or generate FPGA resource references. The palette in an FPGA VI also includes the Clock-Driven Loop, which you place around the majority of the code on the diagram to control the execution speed of that code on the FPGA.
Search within the programming environment to access the following lessons: Programming with Clock-Driven Logic