Import third-party HDL IP that you can use in Clock-Driven Logic within an FPGA application.
Complete the following steps to import HDL source files or files conforming to the IP-XACT standard.
This procedure walks you through selecting and configuring external IP files. For additional information on the user interface of the external IP document, refer to the External HDL IP Document topic linked at the bottom of this topic.
Add a new EIP document to an FPGA target in SystemDesigner by selecting Add Software and then External HDL IP. These locations in SystemDesigner are shown in the following image.
After you select External HDL IP, a new EIP document is created. Within the EIP document, you will select and configure the external IP files.
If you are importing an HDL source file, complete the steps below. If you are connecting an IP-XACT file, proceed to step 3.
In the Main Synthesis Entity section, use the browse button to the right of the File field to select a supported file type to import into the EIP menu. This should be your top-level source file for synthesis.
Use the Parse and Verify button (
), located in the toolbar, to populate the EIP menu with your IP data.
In the Main Simulation Entity section, use the browse button to the right of the File field to select a top-level simulation file.
If the Main Synthesis Entity is a VHDL source file, then the same file will automatically be added to the Main Simulation Entity. You can change the simulation file, but the top-level synthesis file must contain the same entity information as the top-level simulation file. Other files, such as netlists, will not be added to the Main Simulation Entity as this needs to be in the form of a .vhd file.
In the Additional Resources section, use the + button to add supplementary source files.
Modify your signals by highlighting a signal and editing the options in the Item tab.
You will need to press the Parse and Verify button if any changes are made in the signal list.
If you are connecting an IP-XACT file, complete the steps below.
Press the Import button and select your file.
Verify that signal and clock configurations have been imported correctly.
Additional configuration may be required of the IP to make the import successful.
After saving your EIP configuration, you can add the document to a diagram in your FPGA code from the
tab or from the
palette. The node can only be placed within Clock-Driven Logic as shown in the following image.
Refer to the
tab in the software for examples that demonstrate importing external HDL IP. These can be found under the path