Global Registers (Clock-Driven Logic)

Specifies a read or write register instruction. This parameter is usually obtained from the register instruction parameter of the Process node in the Register Bus FPGA library. The source of this parameter defines the instances of the Register Bus library to which the Config library instance is wired, and is communicated from the host.

Indicates whether the register read operation is complete, and returns the data from the register read. Wire this parameter through either a shift register or a feedback node back to the read completion parameter on the Process node of the Register Bus.

A Boolean that indicates whether the register read operation is complete.