Provides built-in support for 5 formats and 3 range standards.The implementation is a simplified 3x3 constant coefficient matrix multiplier, which uses only 4 multipliers exploiting the inter-relations of RGB to YCrCb coefficients. The module is optimized to take advantage of multiply-add capabilities of DSP slices.
In the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Interface: AXI4-Stream, AXI4-Lite
Where This Node Can Run:
Desktop OS: none
FPGA: All devices