Retrieve Data from DRAM (Clock-Driven Logic)

Reference to a DRAM memory item.

Boolean value that specifies whether downstream nodes are ready for this node to return a new value.

Use Feedback Node to wire ready for input of a downstream node to ready for output of the current node. If this input is False during a given cycle, output valid returns False during that cycle.

True	The downstream node is ready for the next data point.
False	The downstream node is not ready for the next data point.

Default: False

Reference to a DRAM memory item.

The data this node retrieves from the DRAM memory on the FPGA target.

Boolean value that indicates whether this node computes a result that downstream nodes can use.

Wire this output to input valid of a downstream node to transfer data from the node to the downstream node.

True	Downstream nodes can use the result this node computes.
False	This node returns an undefined value that downstream nodes cannot use. Note   This node may return different undefined values when executed in simulation mode versus when executed on hardware.