Retrieve Data from DRAM (Clock-Driven Logic)

Reference to a DRAM memory item.

A Boolean that specifies whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

True	The downstream node is ready for the next data point.
False	The downstream node is not ready for the next data point.

Default: TRUE

Reference to a DRAM memory item.

The data this node retrieves from the DRAM memory on the FPGA target.

A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

True	The node has computed a result that downstream nodes can use.
False	This node has not computed a result that downstream nodes can use. Any data output returns an undefined value. The undefined value returned by a data output may differ between simulation and hardware.