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High Throughput Sine and Cosine (Clock-Driven Logic)

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Last Modified: September 10, 2016

Computes both the sine and cosine of a specified value (x). You must specify x in pi radians, which use fewer FPGA resources than radians. To convert a radian value to pi radians, multiply the value by pi.

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x

An input to this operation.

You must specify this input in pi radians, which use fewer resources than radians. To convert radians to pi radians, multiply the radian value by pi.

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input valid

A Boolean that describes whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

TRUE The next data point has arrived for processing.
FALSE The next data point has not arrived for processing.
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ready for output

A Boolean that specifies whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

True The downstream node is ready for the next data point.
False The downstream node is not ready for the next data point.
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Note  

If this input is False during a given cycle, output valid returns False during that cycle.

Default: TRUE

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sin(x)

Result of the operation in pi radians, which uses fewer resources on the FPGA.

This output assumes the same numeric representation as x. When x is of the form x = a + b i, that is, when x is complex, the following equation defines sin:
sin ⁡ ( x ) = sin ⁡ ( a ) * cosh ⁡ ( b ) + i ( cos ⁡ ( a ) * sinh ⁡ ( b ) )
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cos(x)

Result of the operation in pi radians, which uses fewer resources on the FPGA.

This output assumes the same numeric representation as x. When x is of the form x = a + b i, that is, when x is complex, the following equation defines cos:
cos ⁡ ( x ) = cos ⁡ ( a ) * cosh ⁡ ( b ) + i ( − sin ( a ) * sinh ⁡ ( b ) )
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output valid

A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

True The node has computed a result that downstream nodes can use.
False This node has not computed a result that downstream nodes can use. Any data output returns an undefined value. The undefined value returned by a data output may differ between simulation and hardware.
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ready for input

A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

True The node is ready to accept new input data.
False The node is not ready to accept new input data.
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Note  

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

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