Converts polar coordinates to rectangular coordinates. You must specify the phase of the polar coordinates in pi radians, which use fewer FPGA resources than radians. To convert a radian value to pi radians, multiply the value by pi.
Phase in pi radians, which use fewer FPGA resources than radians.
This input supports only the fixed-point data type.
Input Coercion
The CORDIC algorithm represents phase internally as a signed fixed-point number with a 1-bit integer word length. The word length of phase must be less than or equal to 64 bits. If you wire a value to phase that has a fractional word length greater than 63 bits, this node rounds off the lower bits to achieve a fractional word length of 63 bits. For example, if you wire a fixed-point data type with a configuration of I60<-5, 55> to phase, this node coerces the configuration to be U58<-5, 53>.
If you wire a fixed-point data type to phase with a fractional word length greater than 63 bits and an integer word length less than -62 bits, this node coerces the configuration to be I1<-62, 63> if the data type is signed. If the data type is unsigned, the coerced configuration is U1<-62, 63>.
Boolean value that specifies whether downstream nodes are ready for this node to return a new value.
Use Feedback Node to wire ready for input of a downstream node to ready for output of the current node. If this input is False during a given cycle, output valid returns False during that cycle.
True | The downstream node is ready for the next data point. |
False | The downstream node is not ready for the next data point. |
Default: False
X value of the rectangular coordinates.
Y value of the rectangular coordinates.
Boolean value that indicates whether this node computes a result that downstream nodes can use.
Wire this output to input valid of a downstream node to transfer data from the node to the downstream node.
True | Downstream nodes can use the result this node computes. |
False | This node returns an undefined value that downstream nodes cannot use. |
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application