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Optimized FPGA VI (Clock-Driven Logic)

Last Modified: August 28, 2017

Represents an instance of an Optimized FPGA VI. This node allows you to use Optimized FPGA VIs inside Clock-Driven Logic. Each instance can be configured to execute at specific clock rates and throughputs.


input valid

A Boolean that determines whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.


ready for output

A Boolean that indicates whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node. If this Boolean is FALSE during a given cycle, output valid returns FALSE during that cycle.


output valid

A Boolean that returns TRUE if this node has computed a result that downstream nodes can use.


ready for input

A Boolean that returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node. If this Boolean returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if input valid is TRUE during the following cycle.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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