Table Of Contents

FIFO Nodes (Clock-Driven Logic)

Last Modified: August 15, 2017

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Clears a target-scoped or VI-defined FPGA FIFO.
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Creates a locally scoped FIFO of the specified input data type and depth.
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Gets various properties associated with the selected FIFO.
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Empties data from the FIFO and sends the data to the recipient. For DMA target-to-host FIFOs, the recipient is the host. For peer-to-peer writer FIFOs, the recipient is the peer-to-peer reader FIFO.
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Returns the top element of a FIFO without removing it.
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Reads and removes the oldest element from the FPGA FIFO.
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Writes an element to an FPGA FIFO.

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