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Fast Fourier Transform (Clock-Driven Logic)

Last Modified: August 7, 2018

Computes the Discrete Fourier Transform (DFT). The FFT Core can compute 8 to 65536-point forward or inverse complex transforms on up to 12 parallel channels. The input data is a vector of complex values represented as two's-complement numbers 8 to 34 bits wide or single-precision, floating-point numbers 32 bits wide. The phase factors can be 8 to 34 bits wide. All memory is on-chip using either Block RAM or Distributed RAM. Three arithmetic types are available: full-precision unscaled, scaled fixed-point, and block-floating point. Several parameters are run-time configurable: the point size, the choice of forward or inverse transform, and the scaling schedule. Four architectures are available to provide a tradeoff between size and transform time.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4-Stream

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Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application


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