Delays the input value by a specified value.This node supports scalar and array values of integer, fixed-point, and Boolean data types, clusters, and arrays of clusters.
Index of the internal register whose value reaches the Q output. The value of n-1 can be between 0 and n-1, where n is the value of Maximum Delay on the Item tab.
Settings for the initial values of the internal registers this node uses.
A Boolean that indicates whether this node ignores the input to D.
|TRUE||This node shifts all values to the next internal register and takes in a value of D to the first internal register.|
|FALSE||This node ignores D and does not shift existing values, which means the internal registers retain the value they had during the previous clock cycle.|
Use this input to operate on only valid values of D. For example, you can wire the output valid output of High Throughput Math nodes to this input. In this situation, Discrete Delay takes in a value of D only if the incoming value is valid.
Delayed value of D. Q returns the value of the register you specify with the n-1 input.
Discrete Delay and the Feedback Node are similar but have some key differences. The following table provides recommendations for choosing between the two nodes.
|Feedback Node||Discrete Delay||Recommendation|
|Design and features||Designed for||Designed for delaying an input signal by a constant or variable number of clock cycles.||Use the node that represents the use case you are programming.|
|Initialization options||Initialize internal registers to custom values in the following situations:||Discrete Delay implements delays by using shift register lookup tables (SRLs) instead of flip-flops. SRLs combine many delays into a single lookup table (LUT), which can reduce FPGA resource usage significantly compared to flip-flops.|
|Ways of defining initial values||You define initial values by wiring a value to the initial values input on the diagram.||You define initial values by using the initial values input.||Use Discrete Delay if you have an initialization VI or if you need to delay a fixed-size array.|
|Support for dynamic delay||No||Yes||Use Discrete Delay if you need a dynamic delay.|
|Support for representing feedback on a block diagram||Yes||No||Use the Feedback Node if you need to represent feedback on a block diagram.|
This node implements delays by using shift register lookup tables (SRLs) instead of flip-flops. SRLs combine many delays into a single lookup table (LUT), which can reduce FPGA resource usage significantly compared to flip-flops.
This node can increase simulation run time significantly when you use it in conjunction with downloading, stopping, or running the FPGA VI.
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application