# Signed (Clock-Driven Logic)

Version:
Last Modified: September 10, 2016

Implements an adder-subtractor that operates on bit patterns. You can cascade and pipeline AddSub nodes to achieve higher throughput rates.

## carry in/inverted borrow in

A Boolean that determines whether this node accounts for an additional least-significant bit (LSB).

 True Adds one extra LSB to x + y when sub? is False. Computes x – y normally when sub? is True. False Subtracts one extra LSB from x – y when sub? is True. Computes x + y normally when sub? is False.

Default: False

## bypass x

A Boolean that determines whether this node ignores the value you wire to x.

 True This node uses a value of 0 instead of the value you wire to x. False This node uses the value you wire to x.

Use this Boolean to remove x from the expression this node calculates. For example, use this Boolean to return –y instead of xy.

Default: False

## sub?

A Boolean that determines whether this node performs subtraction or addition. Use this Boolean to change the operation of this node programmatically.

 True The node calculates x - y. False The node calculates x + y.

Default: False

## x

An input to this node.

This input supports scalar values of integer and fixed-point data types.

## y

An input to this node.

This input supports scalar values of integer and fixed-point data types.

## overflow

A Boolean that indicates if the theoretical computed value of the sum exceeds the valid range of its data type.

 True This node wraps the value of sum. False This node does not wrap the value of sum.
Note

If you cascade nodes, you must use unsigned versions of the nodes in the intermediate operations. Set the encoding of the final node to the encoding you want for the entire cascaded operation.

## sum

The result this node computes. The result depends on not only the values of x and y but also the values of any Boolean inputs.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices