Applies a digital frequency shift to the I/Q data.
A numerically-controlled oscillator (NCO) creates a cosine/sine pair, which is then multiplied by the I/Q data using a complex multiplier. The net effect is to shift the complex spectrum to the left or right in the frequency domain. You must use this node inside a Clock-Driven Loop. This node provides the following functionality:
, where represents scalar multiplication. The frequency shift input may be in the range of [-0.5 to +0.5), where negative values shift the complex spectrum to the left and positive values shift the complex spectrum to the right. The amount of frequency shift (in Hz) is determined by multiplying the data rate (in Hz) by the frequency shift input. . The data rate is defined by the clock frequency of the Clock-Driven Loop (CDL), the number of samples in data in and data out, and the fraction of cycles on which input valid is asserted. . For example, if the Clock-Driven Loop is clocked at 120 MHz, the node instance selected is 1 sample per cycle (SPC) and the input valid signal is asserted on every other cycle, then the data rate is 60 MHz. The phase input may be in the range of [-0.5 to +0.5), which corresponds to phase shifting the sine and cosine signals -180 degrees to +180 degrees.
Samples Per Cycle (SPC)—On the Item tab, change the number of parallel samples used on the data in and data out terminals. For multiple samples per cycle, data in and data out become fixed size arrays of SPC elements. The first element, data, is the oldest sample in the array.
Overflows—Overflows on data in.overflow are pipelined along with the data path, combined with overflows that occur inside of this node, and output on data out.overflow.
Reset—Toggling the reset input high resets the registers in the output valid path, allowing for deterministic startup behavior. The registers in the data out path are not reset; however, output valid is held low while reset is asserted and does not assert after reset until the registers in the data out path have been flushed. While reset is asserted, ready for input is held low and input valid is ignored.
|Pipeline delay||13 clock cycles|
|Approximate resource usage in a Xilinx Virtex-5 FPGA or Virtex-6 FPGA|
|Approximate maximum clock rate in a Xilinx Virtex-5 FPGA or Virtex-6 (-1) FPGA||160 MHz|
Where This Node Can Run:
Desktop OS: none
FPGA: All devices