Table Of Contents
Detect Falling Edge (Clock-Driven Logic)
Last Modified: September 10, 2016
Detects a transition from TRUE to FALSE on the input signal. Use Detect Falling Edge inside a Clock-Driven Loop.
signal
The signal in which to detect a TRUE to FALSE transition.
edge detected
A Boolean that indicates whether a TRUE to FALSE transition is detected on the input signal.
Where This Node Can Run:
Desktop OS: none
FPGA: All devices