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Interrupt (G Dataflow)

Last Modified: January 12, 2018

Communicates to the host VI that a specific interrupt occurred.

This node asserts an interrupt on the interrupt line of the FPGA target. Since this node is a shared resource, multiple uses of it induce additional delay and jitter due to arbitration. To handle the interrupts in the host VI, use the Wait on Interrupt(s) and Acknowledge Interrupt(s) nodes.

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interrupt number

Number that specifies which interrupt to assert.

Typical supported values are 0 through 31 unless the target documentation specifies otherwise.

Default: 0

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wait until acknowledged

Boolean value that specifies if this node waits until the host VI acknowledges the interrupt or if this node asserts the interrupt and continues.

True This node waits until the host VI acknowledges it.
False This node asserts the interrupt and continues.

Default: False

Where This Node Can Run:

Desktop OS: Windows

FPGA: All devices

Web Server: Not supported in VIs that run in a web application


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