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Adjusting the Settings of an Optimized FPGA VI to Meet Performance Requirements

Last Modified: January 2, 2018

If you estimate an Optimized FPGA VI and find that the design does not meet your performance requirements, or if an Optimized FPGA VI does not compile successfully, adjust the routing margin, resource budget, and clock rate to improve the results.

  1. Access the routing margin, resource budget, and clock rate settings using either of the following methods:
    • Select an Optimized FPGA VI integration node from the diagram of a top-level FPGA VI. On the Item tab, click Advanced, and use the estimation options in the Directed Optimization Settings dialog box.
    • Open an Optimized FPGA VI. On the Document tab, click FPGA Estimates to open the VI Estimation dialog box. Use the estimation options on the Advanced tab.
  2. Raise the routing margin of the Optimized FPGA VI.

    A higher routing margin improves performance results by allowing more time for routing delays between the logic elements on the FPGA. Allowing more time for routing delays tends to increase the number of pipeline stages in the design, which in turn results in a higher achievable clock rate.

  3. Adjust the resource budget of the Optimized FPGA VI.

    If the Optimized FPGA VI utilizes too many FPGA resources, you can decrease the resource budget to make those resources available for other parts of the application. If the Optimized FPGA VI was previously constrained, you can increase the resource budget to achieve a higher throughput rate for the design.

  4. Estimate the Optimized FPGA VI.
  5. (Optional) If adjusting the routing margin and resource budget fails to improve the results, increase or decrease the clock rate. A design that fails to compile due to timing violations may compile successfully at a different clock rate.

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