Table Of Contents

Instantiating External FPGA IP in an FPGA Application using the External FPGA IP Node

Version:
    Last Modified: January 11, 2018

    Integrate external FPGA IP into your FPGA application by placing the External FPGA IP Node into Clock-Driven Logic within your FPGA VI.

    Before you can add the External FPGA IP Node to your FPGA application, you need to declare your IP by creating an External FPGA IP document. Refer to Creating an External FPGA IP Document from IP Source Files or Creating an External FPGA IP Document from an IP-XACT File for help declaring IP for use in your FPGA project.
    1. Locate the EIP file in the Project Files tab and drag it to the diagram. The EIP file becomes the External FPGA IP Node when you place it on the diagram.
    2. Wire the External FPGA IP Node according to the requirements of your application. Note the following behaviors of the External FPGA IP Node:
      • The inputs and outputs of the External FPGA IP Node correspond to signals defined in the External FPGA IP document with the following exceptions:
        • The External FPGA IP Node does not display reset signals.
        • The External FPGA IP Node does not display clock signals unless you configure one clock signal as the Associated clock for another. For example, if you select ClkA as the Associated clock for ClkB, the External FPGA IP Node will display ClkB as an input. You can wire a derived clock to that input.
      • The data type of each input and output is the data type you specify for it in the parent EIP document.
    3. (Optional) Select the External FPGA IP Node. On the Item tab, configure inputs and outputs according to the requirements of your application. You can change the configuration of an External FPGA IP Node instance without affecting the EIP document or any other External FPGA IP Node or CLIP instance built from the same EIP document.

    The following image shows an example of the External FPGA IP Node wired inside a Clock-Driven Loop.

    spd-note-note
    Note  

    Because the inputs and outputs of the External FPGA IP Node reflect the port configurations you make in the EIP document, your results may not match the image above.


    Recently Viewed Topics