Table Of Contents

External FPGA IP Instantiation

Version:
    Last Modified: January 11, 2018

    You can instantiate external FPGA IP in your FPGA application using either component-level IP (CLIP) or the External FPGA IP Node.

    Component-Level IP

    Use component-level IP (CLIP) to import existing IP into FPGA hardware and communicate with it through the interface you create on the FPGA VI diagram. Once imported, the IP runs independently and in parallel with FPGA VI execution. The IP can be in the form of either raw VHDL or intermediate files such as electronic design interchange format (EDIF) netlists.

    You can use CLIP to perform the following tasks:
    • Run external FPGA IP in parallel with FPGA VI code.
    • Execute external FPGA IP in multiple clock domains.
    • Include constraints in the FPGA bitfile compilation.
    • Create CLIP clocks.
    Support for CLIP varies by FPGA target. Refer to the hardware documentation for the target for information about CLIP support.
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    Note  

    In order to achieve the best results with CLIP, National Instruments recommends familiarizing yourself with VHDL.

    Constraints and Hierarchy

    For constraints on specific ports within CLIP, you need to include macros that specify the location of the port within the overall VHDL hierarchy.

    During bitfile compilation, the compiler applies the constraint by replacing the macro with its corresponding value. In addition, the compiler merges the content of the XDC constraint file you create into the top level XDC file it generates for all builds.

    Macro Value
    %ClipInstanceName% The Label you specify for a CLIP instance when you create it in the Resource Collection.
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    Note  

    During compilation, the compiler may modify characters in the CLIP Label to ensure it adheres to VHDL syntax.

    %ClipInstancePath% The hierarchy from the target top-level VHDL to the CLIP top-level VHDL.

    The following XDC code is an example implementation of these macros in a constraint on a CLIP port. In this example, the port in the target top-level VHDL is a clock named clk.

    create_clock -period 10.000 -name %ClipInstanceName%Clk -waveform {0.000 5.000} -add [get_pins %ClipInstancePath%/clk]

    External FPGA IP Node

    Use the External FPGA IP Node to instantiate external FPGA IP on the diagram of an FPGA VI. The External FPGA IP Node executes within Clock-Driven Logic, which runs in a Clock-Driven Loop according to the dataflow of the VI. As part of the dataflow execution, the External FPGA IP Node gives you the ability to verify the overall application behavior and timing using the cycle-accurate simulation tools.

    Choosing between CLIP or the External FPGA IP Node when Instantiating External FPGA IP

    The purpose of the application and your programming preferences determine whether you should use CLIP or the External FPGA IP Node. For example, if you want to simulate your FPGA code before compiling it to a bitfile, use the External FPGA IP Node to instantiate your FPGA IP.
    Use the following table to select the ideal approach for instantiating external FPGA IP.
    Component-Level IP External FPGA IP Node
    Supported synthesis file types Top-level:
    • VHDL (.vhd)
    • Xilinx Synthesis Technology Netlist (.ngc)
    • EDIF Netlist (.edif, .edf, .edn)
    • Design Checkpoint (.dcp)
    • Xilinx Core Instance (.xci)
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    Note  

    XST Netlist (.ngc) files are supported only on Xilinx 7-series FPGA chips.

    Top-level:
    • VHDL (.vhd)
    • Xilinx Synthesis Technology Netlist (.ngc)
    • EDIF Netlist (.edif, .edf, .edn)
    • Design Checkpoint (.dcp)
    • Xilinx Core Instance (.xci)
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    Note  

    XST Netlist (.ngc) files are supported only on Xilinx 7-series FPGA chips.

    Additional:
    • VHDL (.vhd)
    • Xilinx Synthesis Technology Netlist (.ngc)
    • EDIF Netlist (.edif, .edf, .edn)
    • Design Checkpoint (.dcp)
    • Xilinx Core Instance (.xci)
    • Data (.data)
    • Xilinx Distributed Arithmetic FIR Filter Coefficient (.coe)
    • Block RAM Memory Map (.bmm)
    • Xilinx Design Constraints (.xdc)
    Additional:
    • VHDL (.vhd)
    • Xilinx Synthesis Technology Netlist (.ngc)
    • EDIF Netlist (.edif, .edf, .edn)
    • Design Checkpoint (.dcp)
    • Xilinx Core Instance (.xci)
    • Data (.data)
    • Xilinx Distributed Arithmetic FIR Filter Coefficient (.coe)
    • Block RAM Memory Map (.bmm)
    Support for simulation No Yes
    Supported simulation file types N/A Top-level: VHDL (.vhd)
    Additional:
    • VHDL (.vhd)
    • Xilinx Distributed Arithmetic FIR Filter Coefficient (.coe)
    • Memory Initialization File (.mif)
    • Configuration (.cfg)
    • Xilinx Core Instance (.xci)
    Supported data types
    • Boolean
    • Boolean array
    • Integer
    • Fixed-point
    • Floating-point
    • Boolean
    • Boolean array
    • Integer
    • Fixed-point
    • Floating-point
    Execution model Executes parallel to, and independent of, the dataflow of an FPGA VI Executes within Clock-Driven Logic, which runs in a Clock-Driven Loop according to the dataflow of an FPGA VI
    Place of declaration Declared in a project within an EIP document and instantiated within a Resource Collection Declared in a project within an EIP document and instantiated when placed on the FPGA VI diagram as an IPIN
    Languages that support instantiation
    • G Dataflow
    • Clock-Driven Logic
    Clock-Driven Logic
    Support for multiple clock domains Maximum number of clocks defined by FPGA Maximum of two clocks: a Clock-Driven Loop clock and an FPGA-derived clock, where the derived clock executes at a rate that is an integer multiple of the Clock-Driven Loop clock
    Support for using clocks from the IP as clocks that drive a Clock-Driven Loop Yes No
    Support for VHDL generics Yes Yes
    Support for constraints in the FPGA bitfile compilation Yes No

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