To run code on an FPGA, you must compile the FPGA code into a bitfile that you then deploy to the FPGA. The bitfile transfers all the code and performance requirements of an application to an FPGA target.
Before you begin to compile FPGA code into a bitfile, configure LabVIEW to use the FPGA Compile Cloud Service (recommended) or an FPGA compile farm.
Complete the following steps to compile your FPGA code into a bitfile:
In SystemDesigner, add an application to the FPGA target.
In the Create Application dialog box, enter values in Application name and Namespace. Click OK.
In the Application document, click New on the document toolbar and select the type of FPGA VI to create. This VI is the top-level FPGA VI that represents a bitfile and serves as the container for your overall FPGA application. In the Application document, the FPGA VI contains a checkmark in the Top-level VI checkbox.
Place all of the code that makes up your FPGA application either on the diagram of the FPGA VI directly or within subdocuments that appear on the diagram of the FPGA VI.
In the Application document, on the Document tab, enter information about your application in the Details section. Configure the build settings in the Build section.
Click to save all files.
Click Build (
The bitfile begins compiling immediately. The Build Queue tab shows the status of current and completed compilations.
Do not change any code in your FPGA VI during the diagram analysis stage of compilation. Any changes you make to code during the diagram analysis stage may be reflected in the bitfile. If you want to continue working on code while you wait for the compilation to finish, do so after the diagram analysis stage.
Monitor the compilation of your bitfile to determine whether you need to make changes to your code.