Table Of Contents

Run FPGA Simulation (G Dataflow)

Version:
    Last Modified: August 28, 2017

    Simulates the specified Clock-Driven Logic (CDL) document on a host computer. This node simulates one clock period, or one iteration of a Clock-Driven Loop, per execution of the node.

    connector_pane_image

    Retaining Data between Executions

    If you place this node in a loop, each execution of this node advances time within the simulation and updates stateful code, such as Feedback nodes, memory, or FIFOs, inside the CDL document. When you stop the host VI, the CDL document resets and the Run FPGA Simulation node does not carry over any state from the previous execution of the host VI to the next execution.

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: Not supported

    Web Server: Not supported in VIs that run in a web application


    Recently Viewed Topics