Represents an instance of a Multirate diagram.
Clock to control execution.
In addition to the default parameters of the Multirate Diagram node, the node also outputs a FIFO reference for each data port on the multirate diagram.
The Multirate Diagram node behaves differently in a VI targeted to an FPGA than in a VI targeted to a host. If you call a Multirate diagram from a VI targeted to an FPGA, the Multirate Diagram node outputs a FIFO reference for each port on the Multirate diagram, including input ports.
Where This Node Can Run:
Desktop OS: Windows
FPGA: All devices (only within an Optimized FPGA VI)
Web Server: Not supported in VIs that run in a web application