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Multirate Diagram (FPGA Target) (G Dataflow)

Version:
    Last Modified: August 28, 2017

    Represents an instance of a Multirate diagram.

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    Clock

    Clock to control execution.

    Additional Parameters

    In addition to the default parameters of the Multirate Diagram node, the node also outputs a FIFO reference for each data port on the multirate diagram.

    FIFO References

    The Multirate Diagram node behaves differently in a VI targeted to an FPGA than in a VI targeted to a host. If you call a Multirate diagram from a VI targeted to an FPGA, the Multirate Diagram node outputs a FIFO reference for each port on the Multirate diagram, including input ports.

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: All devices (only within an Optimized FPGA VI)

    Web Server: Not supported in VIs that run in a web application


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