Table Of Contents

FPGA Host Interface Nodes (G Dataflow)

Version:
    Last Modified: January 12, 2018

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    Aborts the opened and running FPGA VI on the simulated FPGA target.
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    Communicates to the FPGA VI that the host VI received the interrupt(s).
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    Requests a region to read from the Target to Host FIFO and returns an external data value reference to this region. Use this node to automatically begin DMA data transfer between the FPGA target and the host computer without using Start DMA FIFO.
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    Requests a region to write to a Host to Target FIFO and returns an external data value reference to this region. Use this node to automatically begin DMA data transfer between the FPGA target and the host computer without using Start DMA FIFO.
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    Closes the reference to the FPGA VI.
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    Specifies the capacity, or depth, in elements of the Host to Target FIFO.
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    Downloads the specified FPGA VI or bitfile to the FPGA target.
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    Casts the input reference to the specified data type.
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    Returns the execution mode of the FPGA VI.
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    Opens a reference to an FPGA bitfile and FPGA target you specify or an FPGA application in simulation.
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    Reads elements of a Target to Host FIFO from a VI targeted to an FPGA.
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    Reads and writes values to controls or indicators in the FPGA VI on the FPGA target.
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    Reserves the specified PXI trigger line.
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    Runs the FPGA VI on the FPGA target.
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    Begins DMA data transfer between the FPGA target and the host computer.
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    Ends the DMA data transfer between the FPGA target and the host computer.
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    Unreserves the specified PXI trigger line.
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    Waits for any number of interrupts you included in the compiled FPGA VI running on the FPGA target.
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    Writes data to a Host to Target FIFO from the host VI.
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    Transfer data from one target directly to another using peer-to-peer streaming.

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