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Xilinx Signal Generation Nodes (Clock-Driven Logic)

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    Last Modified: August 15, 2017

    Implement IP related to signal generation.

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    Creates up counters, down counters, and up/down counters with output widths ranging up to 256 bits.
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    Provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores.

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