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Xilinx IP Data Storage (Clock-Driven Logic)

Last Modified: August 15, 2017

Implement IP related to FIFOs, RAMs, and ROMs.

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Replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. Use this generator in all new Xilinx designs.
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Creates area and performance optimized ROM blocks, single and dual port distributed memories, and SRL16-based memories for Xilinx FPGAs.
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Generates resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.
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Generates fast, compact FIFO-style registers, delay lines, or time-skew buffers up to 256 bits wide and up to 1024 words deep using Select RAM in SRL16 or SRLC32 mode.

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