Implements many different Reed-Solomon coding standards. The core is fully synchronous, using a single clock, and supports continuous input data with no gap between code blocks. The core is parameterizable, allowing you to control the symbol size, the code block length, the number of errors corrected, and the control signal behavior. The Decoder supports both error and erasure decoding. It is delivered through the Xilinx CORE Generator system and integrates with the Xilinx design flow.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: Yes
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application