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High Throughput Reciprocal (Clock-Driven Logic)

Last Modified: September 14, 2017

Computes 1/x.

This node rounds the result by truncating the value of the 1/x output terminal towards 0. This rounding mode uses fewer FPGA resources than other rounding modes do.

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x

Input to this operation. If the value of x is 0, overflow occurs in the 1/x output terminal.

This input supports only scalar values of the fixed-point data type.

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operation overflow

A Boolean that indicates whether the theoretical computed value exceeds the valid range of the output data type.

TRUE The theoretical computed value exceeds the valid range of the output data type.
FALSE The theoretical computed value does not exceed the valid range of the output data type.
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1/x

1/x.

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input valid

Boolean value that specifies whether the next data point is valid and can be processed.

Wire output valid of an upstream node to this input to transfer data from the upstream node to this node.

True The data point is valid and can be processed.
False The data point is not valid.
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ready for output

Boolean value that specifies whether downstream nodes are ready for this node to return a new value.

Use Feedback Node to wire ready for input of a downstream node to ready for output of the current node. If this input is False during a given cycle, output valid returns False during that cycle.

True The downstream node is ready for the next data point.
False The downstream node is not ready for the next data point.

Default: False

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output valid

Boolean value that indicates whether this node computes a result that downstream nodes can use.

Wire this output to input valid of a downstream node to transfer data from the node to the downstream node.

True Downstream nodes can use the result this node computes.
False This node returns an undefined value that downstream nodes cannot use.
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Note  

This node may return different undefined values when executed in simulation mode versus when executed on hardware.

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ready for input

Boolean value that indicates whether this node is ready to accept new input data.

Use Feedback Node to wire this output to ready for output of an upstream node.

True The node is ready to accept new input data.
False The node is not ready to accept new input data.
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Note  

If this output returns False during a given cycle, this node discards any data that other nodes send to this node during the following cycle. This node discards the data even if input valid is True during the following cycle.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application


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