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Host Driven Synchronization (G Dataflow)

Last Modified: January 9, 2017

Use this flavor of synchronization in conjunction with Host Align on the FPGA. When this node finishes, the FPGAs are synchronized.

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error in

Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.

Default: No error

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error out

Error information. The node produces this output according to standard error behavior.

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sync.cptr.period

The period (in clocks) of the common periodic time reference (CPTR). The default value automatically sets the CPTR period to 10 MHz. The CPTR period controls the rate at which synchronized signals are realized. When you use FPGA Align, the CPTR period must be the same as the Reference Clock period. The sync.cptr.period must be set to the ratio of the clock-driven loop (CDL) rate that the Align node is in to the common reference rate. For example, the CPTR period must be 12 if using a 10 MHz Reference Clock, and the Data Clock for the CDL Clock (120 MHz/10 MHz). When you use Host Align, this value is configurable. The maximum value is 63. The minimum value for the sync.cptr.period must be big enough to ensure transmission across the sync.fpga io line. Refer to the specifications for the FPGA I/O line chosen. For example, if the FPGA I/O line has a maximum propagation delay of 50 ns, the minimum value is 6. Because the period of the 120 MHz Data Clock is ~8.333 ns, it would require 6 clock periods to exceed 50 ns. NI does not recommend changing the CPTR period while running. Alignment must be re-run if the CPTR period is changed.

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niUsrpRio Sessions (out)

niUsrpRio sessions used in all subsequent USRP RIO host nodes.

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niUsrpRio Sessions

Objects created by the Open node and used as the session handles for the USRP RIO nodes.

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported


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