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Transferring Data to Deterministic Code

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    Last Modified: September 20, 2016

    Data transfer to deterministic code requires the use of a communication method designed specifically for real-time (RT) applications. Other communication methods, such as queues, TCP, and UDP use variable size buffers and do not transfer data deterministically. Use the RT FIFO nodes to transfer data to and receive data from deterministic code.

    What to Use

    What to Do

    Create the following diagram to transfer data between two loops in a real-time VI using RT FIFOs.

    Customize the gray sections for your unique programming goals.

    RT FIFOs ensure deterministic behavior by preallocating memory for the data and imposing a size restriction on the data you share. The RT FIFO Create node allocates a section of memory on the RT controller to create an RT FIFO. If you know your application requires a buffer size of more than the default size of 10 elements, configure the size as a number of elements that prevents data loss.
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    Tip  

    If you do not know how many elements the buffer needs to hold, you can adjust the size when you benchmark your application.

    If you want to use the RT FIFO that you create to transfer data between loops in separate VIs, you can use one of the following methods:

    • Use Create RT FIFO in the top-level VI in your RT application and then wire rt fifo into multiple subVIs on the diagram.
    • If you do not want to use wires, you can use a string constant and the name input of RT FIFO Create. Naming an RT FIFO that you create in the top-level VI of your RT application allows you to call a reference to an existing RT FIFO using the same name in a subVI. An example of the code that you would use to create and call a reference to an RT FIFO is shown in the following image.
    When you use RT FIFO Write in a loop, it writes a value for every iteration of the Timed Loop. If the RT FIFO is full, RT FIFO Write overwrites the oldest value in the RT FIFO.
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    Note  

    You can prevent the node from overwriting the oldest value and ensure that no data is lost by using timeout in ms to configure RT FIFO Write to wait for space to become available.

    If your application does not require that you receive a new value from the RT FIFO for every iteration of the Timed Loop, you can use a Feedback Node with RT FIFO Read instead of configuring timeout in ms and monitoring empty?. Wire a reverse Feedback Node to element and element out so RT FIFO Read produces data using the previous value if there is no new value available in the RT FIFO. In this diagram, RT FIFO Read uses the value from the previous iteration if Amplitude does not write a new value to the RT FIFO.
    Configure the timeout in ms input of RT FIFO Read to wait infinitely for a new value from the Timed Loop.

    If this timing configuration causes high CPU usage in your application, consider using a Wait node in the While Loop that is configured to wait for longer than the period of the Timed Loop.

    Create a safe shutdown process by using Stopped Timed Structure to abort the Timed Loop when the While Loop stops executing due to an error or user action. Stopping the execution of the Timed Loop directly from a user control can result in execution aborting during unknown conditions.
    For example, if the application controls a piece of equipment and the stop control in the While Loop is wired to the part of your application that monitors conditions, the equipment can stop when conditions are not ideal.
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    Note  

    Stop Timed Structure does not stop the Timed Loop if error in contains an error, so you should use Clear Error Cluster to clear errors from the error wire.

    Delete the reference to the RT FIFO to release the memory resources allocated on the RT controller when you created the reference. Because of the nature of dataflow, the error wire ensures that RT FIFO Delete executes after the Timed Loop stops.
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    Note  

    RT FIFO Delete does not delete the reference if error in contains an error, so you should use Clear Error Cluster to clear errors from the error wire.

    Troubleshooting

    • If the application stops producing data but does not abort execution, you may need to update the configuration of one of the RT FIFO nodes:
      • If you configured RT FIFO Write in the Timed Loop to wait until space becomes available instead of writing over the oldest value in the RT FIFO, use the size input of RT Create FIFO to increase the buffer size of that RT FIFO.
      • If you configured RT FIFO Read in the While Loop to wait infinitely and the Timed Loop stopped producing data, use a timing node to control the timing of the While Loop instead.

    Examples

    Search LabVIEW for the following installed example: Using the Timed Loop with RT FIFOs

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