Create the following diagram to transfer data between two loops in a real-time VI using RT FIFOs.
Customize the gray sections for your unique programming goals.
| RT FIFOs ensure deterministic behavior by preallocating memory for the data and imposing a size restriction on the data you share. The RT FIFO Create node allocates a section of memory on the RT controller to create an RT FIFO. If you know your application requires a buffer size of more than the default size of 10 elements, configure the size as a number of elements that prevents data loss.
If you want to use the RT FIFO that you create to transfer data between loops in separate VIs, you can use one of the following methods:
|When you use RT FIFO Write in a loop, it writes a value for every iteration of the Timed Loop. If the RT FIFO is full, RT FIFO Write overwrites the oldest value in the RT FIFO.|
|If your application does not require that you receive a new value from the RT FIFO for every iteration of the Timed Loop, you can use a Feedback Node with RT FIFO Read instead of configuring timeout in ms and monitoring empty?. Wire a reverse Feedback Node to element and element out so RT FIFO Read produces data using the previous value if there is no new value available in the RT FIFO. In this diagram, RT FIFO Read uses the value from the previous iteration if Amplitude does not write a new value to the RT FIFO.|
|Configure the timeout in ms input of RT FIFO Read to wait infinitely for a new value from the Timed Loop.
If this timing configuration causes high CPU usage in your application, consider using a Wait node in the While Loop that is configured to wait for longer than the period of the Timed Loop.
|Create a safe shutdown process by using Stopped Timed Structure to abort the Timed Loop when the While Loop stops executing due to an error or user action. Stopping the execution of the Timed Loop directly from a user control can result in execution aborting during unknown conditions.
For example, if the application controls a piece of equipment and the stop control in the While Loop is wired to the part of your application that monitors conditions, the equipment can stop when conditions are not ideal.
|Delete the reference to the RT FIFO to release the memory resources allocated on the RT controller when you created the reference. Because of the nature of dataflow, the error wire ensures that RT FIFO Delete executes after the Timed Loop stops.|