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Decimate 1D Array (G Dataflow)

Last Modified: January 23, 2017

Divides the elements of an array into multiple output arrays, placing elements into the outputs successively.

This node drops any elements that cause the output arrays to have different lengths.

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array

A 1D array of any type.

Data Type Changes on FPGA

When you add this node to a document targeted to an FPGA, this input has a default data type that uses fewer hardware resources at compile time.

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decimated array

The node stores array[0] at index 0 of the first output array, array[1] is stored at index 0 of the second output array, array[n-1] at index 0 of the last output array, array[n] at index 1 of the first output array, and so on, where n is the number of output terminals for this node.

For example, assume array has 16 elements and that you wire four decimated array outputs. The four output arrays will return the following elements:
  • The first output array contains elements 0, 4, 8, and 12.
  • The second output array contains elements 1, 5, 9, and 13.
  • The third output array contains elements 2, 6, 10, and 14.
  • The last output array contains elements 3, 7, 11, and 15.

If array is not evenly divisible, the remainder is disregarded. For example, assume array has 15 elements and that you wire four decimated array outputs. The four output arrays will return the following elements:

  • The first output array contains elements 0, 4, and 8.
  • The second output array contains elements 1, 5, and 9.
  • The third output array contains elements 2, 6, and 10.
  • The last output array contains elements 3, 7, and 11.

Because the node only returns arrays of the same size, all decimated array outputs drop the last element so that all of the arrays contain 3 elements.

Where This Node Can Run:

Desktop OS: Windows

FPGA: All devices (only within an Optimized FPGA VI)


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