Table Of Contents

Clock-Driven Loop (G Dataflow)

Last Modified: January 9, 2017

Executes the code in the subdiagram within a single cycle of the FPGA target clock or a clock you specify.

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Clock

Clock that controls the loop.

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Iteration

Current loop iteration count. The loop count always starts at zero for the first iteration. If the iteration count exceeds 2,147,483,647, or 231-1, the iteration terminal remains at 2,147,483,647 for all further iterations. If you need to keep count of more than 2,147,483,647 iterations, you can use shift registers with a greater integer range.

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Condition

Determines whether to continue executing the loop. The loop runs infinitely by default. To specify whether the loop stops for a TRUE or FALSE Boolean value, configure the continuation behavior.

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Tunnel

Point through which data enters the structure.

Where This Node Can Run:

Desktop OS: Windows

FPGA: All devices (only within an Optimized FPGA VI)


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