Generates bit sequences based on a pattern that you specify. The node repeats the selected pattern until it generates the number of bits that you specify.
Total number of pseudorandom bits to be generated.
Default: 128
Initial state of the PN generator shift register. If no seed is specified, the default seed is used.
Default: 169
Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.
Default: no error
The base pattern of bits that you specify.
Default: empty
The binary data stream corresponding to the value that you specify in the user base bit pattern parameter.
Though deterministic in nature, seudorandom or pseudonoise (PN) sequences satisfy many properties of random numbers, such as autocorrelation, crosscorrelation, and so on. PN sequences are used in many applications and standards such as 802.11a and DVB. Some examples of PN sequences are maximal length shift register sequences, or m-sequences, Gold sequences, and Kasami sequences. An m-sequence generates a periodic sequence of length $L={2}^{m}-1$ bits and is generated by linear feedback shift registers (LFSRs). Two well known implementations of m-sequences are the Fibonacci implementation and the Galois implementation.
The preceding figure shows the Fibonacci and Galois implementations of m-sequences. As can be seen in these figures, m-sequences contain m shift registers. The shift register set is filled with an m-bit initial seed that can be any value except 0. If the m bits in the m shift registers are all zero, then it is a degenerate case and the output of the generator is 0.
The following examples demonstrate bit generation:
Primitive polynomial: $1+{X}^{14}+{X}^{15}$
Initial seed: 000000010101001
The following figure shows the circuitry:
Seed | Output |
---|---|
000000010101001 | 0+0=0 |
000000101010010 | 0+0=0 |
000001010100100 | 0+0=0 |
000010101001000 | 0+0=0 |
000101010010000 | 0+0=0 |
001010100100000 | 0+0=0 |
010101001000000 | 0+1=1 |
101010010000001 | 1+0=1 |
Primitive polynomial: $1+{X}^{14}+{X}^{15}$
Initial seed: 000000010101001
The circuitry is shown in the following figure:
Seed | Output |
---|---|
000000010101001 | 0 |
000000101010010 | 0 |
000001010100100 | 0 |
000010101001000 | 0 |
000101010010000 | 0 |
001010100100000 | 0 |
010101001000000 | 0 |
101010010000000 | 1 |
110100100000001 | 1 |
001001000000011 | 0 |
010010000000110 | 0 |
100100000001100 | 1 |
101000000011001 | 1 |
110000000110011 | 1 |
000000001100111 | 0 |
000000011001110 | 0 |
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported