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MT Convolutional Interleaver (Standard) (G Dataflow)

Last Modified: January 9, 2017

Performs interleaving using a fixed number of branches and a fixed unit delay.

Each branch has different delays associated with it. Hence, the data input of each interleaver branch is delayed by a specific amount (the amount of delay in that branch) before the interleaver returns the data. A convolutional interleaver is twice as efficient as a block interleaver.


data in

The input data to the interleaver.


number of branches

The number of branches of the convolutional interleaver. Data elements pass through the branches in a cyclic fashion. For example, in an N branch convolutional interleaver, data element 0 goes through branch 0, element 1 goes through branch 1, element N-1 goes through branch N-1, element N returns through branch 0, and so on. Each branch incorporates different delays.

Default: 0


unit delay

The unit delay value. If this value is defined as D, then the number of delays on the ith branch is (i×D). If the total number of branches is N, then i = 0, 1,…, N-1.

Default: 0


initial state

The shift register values when the convolutional interleaver begins operation.


error in

Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.

Default: no error



A Boolean that determines whether to check the current input parameters. The current input parameters are always checked on the first run of this node.

TRUE Checks input parameters.
FALSE Does not check input parameters.

Default: TRUE


data out

The convolutional interleaved data returned by this node.


error out

Error information. The node produces this output according to standard error behavior.

Examples of Convolutional Interleaving and Deinterleaving

The following example demonstrates convolutional interleaving and deinterleaving. Let the data in be: x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, …

Interleaver Input Interleaver Output

D = unit delay in the path.

Assume for this example that the unit delay = 1, and the initial state shift registers are initialized with values of 0 for both the interleaver and the deinterleaver.

Interleaved Data: x0, 0, 0, 0, x4, x1, 0, 0, x8, x5, x2, 0, x12, x9, …

Deinterleaver Input Deinterleaver Output

Deinterleaved Data: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, …

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported

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