Last Modified: January 9, 2017

Performs the deinterleaving process using a fixed number of branches and fixed unit delay.

A convolutional deinterleaver is the inverse of a convolutional interleaver. In convolutional deinterleaving, data elements pass cyclically through a set of branches. That is, in an *N* branch convolutional deinterleaver, the element 0 goes through branch 0, element 1 goes through branch 1, element *N*-1 goes through branch *N*-1, element *N* goes through branch 0, and so on. Each branch has different delays associated with it. Hence the data sent to each deinterleaver branch is delayed by a specific amount (the amount of delay in that particular branch) before the deinterleaver returns the data. In a convolutional interleaver, if the delay in branch number *n* is *d*_{n}, maximum delay is *max_delay* and the minimum delay is *min_delay*, then for the corresponding convolutional deinterleaver, the delay in branch number *n* is: *D*_{n} = (*max_delay*+*min_delay*)-*d*_{n}.

The input data to the deinterleaver.

The number of branches of the convolutional deinterleaver. Data elements pass through the branches in a cyclic fashion. For example, in an *N* branch convolutional deinterleaver, data element 0 goes through branch 0, element 1 goes through branch 1, element *N*-1 goes through branch *N*-1, element *N* returns through branch 0, and so on. Each branch incorporates different delays.

**Default: **0

The unit delay value. If this value is defined as *D*, then the number of delays on the *i*th branch is (*i*×*D*). If the total number of branches is *N*, then *i* = 0, 1,…, *N*-1.

**Default: **0

The shift register values when the convolutional deinterleaver begins operation.

Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.

**Default: **no error

The output of the convolutional deinterleaver.

The following example demonstrates convolutional interleaving and deinterleaving. Let the **data in** be: x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, …

Interleaver Input Interleaver Output

D = unit delay in the path.

Assume for this example that the unit delay = 1, and the initial state shift registers are initialized with values of 0 for both the interleaver and the deinterleaver.

Interleaved Data: x0, 0, 0, 0, x4, x1, 0, 0, x8, x5, x2, 0, x12, x9, …

Deinterleaver Input Deinterleaver Output

Deinterleaved Data: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, …

**Where This Node Can Run: **

Desktop OS: Windows

FPGA: Not supported