If your design allows, use For Loops within an Optimized FPGA VI to enable the compiler to explore a balance of optimizations between throughput and FPGA resource utilization. With loop-based designs, you can increase the throughput rate at the expense of FPGA resources, or you can decrease the throughput rate to save FPGA resources.
The following example demonstrates how loop-based design allows you to explore the tradeoffs between throughput and resource utilization. The IIR filter, FilterCore, is implemented with loop-based design.
The following table demonstrates how prioritizing throughput or resource usages affect each other.
|Clock Rate||Requested Throughput||Initiation Intervals||DSP48 slices|
|100 MHz||100 MegaCalls/second||1 clock cycle||5|
|100 MHz||33 MegaCalls/second||3 clock cycles||2|
If FPGA resources are scarce, you can target the lower throughput rate. If FPGA resources are more plentiful, you can target the higher throughput rate. If you implement the IIR filter without using a For Loop, the difference in FPGA resource utilization between the higher targeted throughput and the lower targeted throughput is not as pronounced because the compiler does not make optimizations related to loop unrolling.
If you have a feedback pattern in your For Loop, as demonstrated in the following image, you might not benefit from the advantages of loop unrolling because the compiler must wait for all loop iterations to complete before providing new inputs. You should avoid loop feedback patterns when possible, with the exception of array shift register initialization. The preceding IIR filter example uses a feedback pattern, but because the data type is an array, the compiler optimizes the initialization of the array to eliminate the iteration dependency.