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Mapping Arrays to Hardware

Last Modified: March 30, 2016

Memory inference is the process by which the compiler recognizes arrays in code and maps those arrays to hardware. The compiler automatically maps arrays in Optimized FPGA VIs to block RAM or to FPGA slices. In general, the compiler maps arrays smaller than 128 bits to FPGA slices and arrays larger than 128 bits to block RAM.

The following list summarizes the advantages and disadvantages of mapping arrays to the two types of FPGA resources:

  • Block RAM—This memory is dedicated only to storing array data. However, block RAM has a limited amount of access bandwidth that is determined by the number of available access ports. Given this limited access bandwidth, the compiler will serialize access to multiple arrays, which can limit the overall throughput.
  • FPGA Slices—FPGA slices allow for accessing multiple arrays in parallel, which results in higher throughput. However, mapping arrays to FPGA slices means fewer FPGA slices are available for other operations, and it also leaves block RAM unused in the hardware implementation.

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