Table Of Contents

Introduction to FPGA Performance

Last Modified: March 30, 2016

When developing an Optimized FPGA VI, consider the performance you want the VI to achieve when it runs on the FPGA. Performance criteria for an Optimized FPGA VI include clock rate, throughput, latency, and the initiation interval.

  • Clock Rate—The clock rate determines the intended execution rate of the individual pieces of code on the diagram.
  • Throughput—The throughput, in MegaCalls/second, is the rate at which the FPGA can provide new inputs to an Optimized FPGA VI.
  • Latency—Latency is the number of clock cycles the FPGA requires between receiving inputs and providing outputs for one call of an Optimized FPGA VI.
  • Initiation Interval—The initiation interval is the number of clock cycles the FPGA requires before it can provide new inputs to an Optimized FPGA VI. The initiation interval is related to clock rate and throughput by the following equation:

    Initiation Interval = Clock Rate / Throughput

The following image provides a visual explanation of the relationship between the Optimized FPGA VI performance directives and achievable performance. If clock rate is 200 MHz, then the performance values are as follows:

  • Throughput is 100 MegaCalls/second.
  • Latency is 6 clock cycles.
  • Initiation interval is 2 clock cycles.

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