Table Of Contents

FPGA Resource Utilization with Optimized FPGA VIs

Last Modified: March 30, 2016

Optimized FPGA VIs require a certain amount of limited resources, such as configurable logic blocks (CLBs) and memory, to execute.

The following table summarizes factors that typically require greater utilization of a particular FPGA resource. For example, increasing the size of arrays in your VI requires greater use of block RAM.


The table lists general trends. To understand the resources your specific VI requires, you must use the estimation tools on your VI.

Resource Utilization Factors Block RAM DSP48 Flip-Flops LUTs
Increasing array size
Increasing multiply and multiply-accumulator operations
Increasing use of Boolean and Numeric nodes
Increasing use of Math nodes
Increasing clock rate
Increasing throughput

In addition to the factors listed in the table, increasing the complexity of your algorithm leads to greater utilization of all FPGA resources. Common design choices that result in more complex algorithms include a high number of nested loops and the use of wider data types, such as 32-bit numbers versus 16-bit numbers.

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