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Estimating FPGA Performance and Resource Usage in Standard Mode

Last Modified: March 30, 2016

The editor provides estimation tools to help you determine the resources your algorithm requires of the FPGA, as well as the performance your algorithm can achieve.


If your algorithm has array inputs or outputs, standard mode provides performance and resource estimates for processing all array elements in one call of the Optimized FPGA VI.

  1. On the Document tab, click FPGA Estimates to display the estimation options.
  2. Specify a desired clock rate and throughput rate. Consider the processing capabilities of your FPGA target and at what frequency you want the algorithm to return outputs.

    These rates are for estimation purposes only. Other parts of the application, such as a top-level VI, ignore the rates you specify within the VI Estimation dialog box.

  3. Select Standard from the Input Mode and Output Mode pull-down menus.
  4. Click FPGA Estimates to perform the estimation.

The estimation results display, without closing the dialog box, in the Algorithm Estimates tab. The following image displays a subset of the tab.

  • Clock Rate—The highest estimated clock rate the Optimized FPGA VI can achieve.
  • Throughput—The throughput is calculated by the following formula: Throughput = Requested Clock Rate/Initiation Interval. If the Optimized FPGA VI has an array input, the entire array is the sample.
  • Latency—The number of clock cycles, in a steady state, that elapse between the Optimized FPGA VI accepting an input and producing the corresponding output.
  • Initiation Interval (II)—The number of clock cycles that must elapse between calls to the Optimized FPGA VI.

If an Optimized FPGA VI has multiple loops, the output interval depends on the loops connected to the output and might not correlate to the initiation interval.

You can use the Advanced tab in the VI Estimation dialog box to access options that provide more precise control of FPGA resource utilization:

  • Routing Margin—The routing margin affects how FPGA resources connect together. If you are having trouble achieving your target clock rate, you can increase the routing margin to achieve better results, but note that increasing the routing margin increases the number of flip-flops your algorithm requires.
  • Resource Budget—Adjust the resource budget sliders to specify what percentage of the total FPGA resources is available for the circuit. By default LabVIEW makes all FPGA resources available in equal proportion. Disable Link resource budgets to specify individual budgets for each FPGA resource.

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