Table Of Contents

Estimating FPGA Performance and Resource Usage in Element-by-Element Mode

Last Modified: March 30, 2016

If you have at least one array input or output, and you have connected the array(s) on the connector pane, you can use element-by-element mode to interface with an Optimized FPGA VI. In element-by-element mode, LabVIEW processes only one element of array inputs or outputs during each call of an instance of an Optimized FPGA VI.
spd-note-note
Note  

If your arrays use auto-indexing at loop boundaries, using element-by-element mode during estimation might provide a performance improvement compared to using standard mode.

  1. On the Document tab, click FPGA Estimates to display the estimation options.
  2. Specify a desired clock rate and throughput rate. Consider the processing capabilities of your FPGA target and at what frequency you want the algorithm to return outputs.
    spd-note-note
    Note  

    These rates are for estimation purposes only. Other parts of the application, such as a top-level VI, ignore the rates you specify within the VI Estimation dialog box.

  3. Select Element-by-element from the Input Mode and Output Mode pull-down menus.
  4. Click FPGA Estimates to perform the estimation.

The estimation results display, without closing the dialog box, in the Algorithm Estimates pane. The following image displays a subset of the pane.

  • Clock Rate—The highest estimated clock rate the Optimized FPGA VI can achieve.
  • Throughput—The throughput is calculated by the following formula: Throughput = Requested Clock Rate/Elemental Initiation Interval. The sample is a single element in the array. You might see the estimated throughput labeled as an average throughput. This labeling typically occurs when the elemental initiation interval multiplied by the array size is greater than the overall initiation interval. In this case, the throughput is calculated by the following formula: Throughput = Clock Rate/(Overall Initiation Interval/Array Size).
  • Latency—The number of clock cycles, in a steady state, that elapse between the Optimized FPGA VI accepting an input and producing the corresponding output.
  • Initiation Interval (II)—The initiation interval displays in the following format: Overall Initiation Interval/Elemental Initiation Interval/[Effective Array Size].
    • Overall Initiation Interval—The number of clock cycles that elapse between the first element of the input arrays on one call of the VI and the first element of the next call to the VI.
    • Elemental Initiation Interval—The number of clock cycles that elapse between elements of input arrays.
    • Effective Array Size—The size of array used for all arrays. The size might be smaller than the largest array in the Optimized FPGA VI if some of the elements of the largest array are not used by the algorithm.
spd-note-note
Note  

If an Optimized FPGA VI has multiple loops, the output interval depends on the loops connected to the output and might not correlate to the initiation interval.


Recently Viewed Topics