You can set desired resource usage and performance directives for an Optimized FPGA VI, and then use the estimation tools to determine if the resource usage and performance can be met before you deploy the code to the FPGA.
You can specify the directives for an Optimized FPGA VI in two locations:
Matching the clock rate of the Optimized FPGA VI to the clock rate of the Clock-Driven Loop that contains the Optimized FPGA VI is a recommended starting point. However, these clock rates do not have to match. Targeting a higher clock rate for the Optimized FPGA VI than the Clock-Driven Loop tends to increase the pipeline stages of the design, which in turn results in a higher achievable clock rate for the surrounding loop.