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Resource and Performance Estimation in Optimized FPGA VIs

Last Modified: March 30, 2016

You can set desired resource usage and performance directives for an Optimized FPGA VI, and then use the estimation tools to determine if the resource usage and performance can be met before you deploy the code to the FPGA.

You can specify the directives for an Optimized FPGA VI in two locations:

  • Within a top-level FPGA VI—Select the Optimized FPGA VI integration node and specify the directives on the Item tab.

    Matching the clock rate of the Optimized FPGA VI to the clock rate of the Clock-Driven Loop that contains the Optimized FPGA VI is a recommended starting point. However, these clock rates do not have to match. Targeting a higher clock rate for the Optimized FPGA VI than the Clock-Driven Loop tends to increase the pipeline stages of the design, which in turn results in a higher achievable clock rate for the surrounding loop.

  • Within an Optimized FPGA VI—Click FPGA Estimates on the Document tab and specify the directives in the dialog.

The compiler does not guarantee a hardware implementation with the exact clock rate and throughput rate that you specify in the directives. For this reason, it is important to estimate an Optimized FPGA VI to determine if the design meets the performance requirements.

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