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Optimized FPGA VIs in Other Document Types

Last Modified: March 30, 2016

After setting the build output of a VI as Optimized FPGA VI and placing the controls and indicators of the Optimized FPGA VI on the connector pane, you can call the Optimized FPGA VI from other document types.

Optimized FPGA VI in a Top-Level VI

To call an Optimized FPGA VI from a top-level VI, you must place the Optimized FPGA VI within a Clock-Driven Loop and wire the handshaking inputs to the node and the clock input to the loop. The following image displays an example of calling an Optimized FPGA VI in a top-level VI.

Optimized FPGA VI in a VI Diagram

To call an Optimized FPGA VI from a VI diagram, you need only place the Optimized FPGA VI on the diagram.

Optimized FPGA VI in a Multirate Diagram

To call an Optimized FPGA VI from a Multirate Diagram, you need only place the Optimized FPGA VI on the diagram.


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