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Testing a Clock-Driven Logic Document on the Host

Last Modified: September 20, 2016

Compiling code for the FPGA can take minutes to hours. To save time, you can test the logic of Clock-Driven Logic documents using simulation in a host VI before compiling. Testing individual Clock-Driven Logic (CDL) documents on the host allows you to ensure that you thoroughly test the functionality of the CDL code. When you deploy a CDL document to an FPGA, as a sub-document of an FPGA VI, it becomes part of the larger FPGA design and it is more difficult to isolate the CDL code for testing.

What to Use

What to Do

Create the following diagram to simulate and test your CDL document in a host VI.

Customize the gray sections for your unique programming goals.

Select a CDL document to simulate with the Run FPGA Simulation node on the Item tab. The inputs and outputs that appear on the node correspond to the inputs and outputs of the CDL document you select.

If there are sampling probes in the CDL document that you select, you can view data for each sampling probe when you simulate using Run FPGA Simulation. To view data, use the Tool Launcher to open the Sampling Probes tab and set Sampling Source to the FPGA to which you targeted the CDL document.

The Run FPGA Simulation node simulates clock cycles on an FPGA. Because code on an FPGA often takes multiple clock cycles to produce valid data, you can use a While Loop around the Run FPGA Simulation node to ensure that the host VI runs until the CDL executes completely.
The For Loop repeats the code you want to test until all the test values you supply are consumed. The auto-indexing functionality of a For Loop allows the CDL document to access and process each individual element of an input array. You can then collect the result of each loop iteration with an auto-indexing output tunnel.
Provide test data that exercises all inputs and outputs of the CDL document and spans the range you expect the CDL document to receive from the application.

The code in the diagram example above focuses on testing the data in input, a cluster, of the CDL document. Depending on your preference, you can test all inputs and outputs in a single host VI or you can test them across multiple VIs.

Provide results you expect the CDL document to produce for the test data provided.
Compare the results of the data processed by the CDL document to the results you expect to determine if logic or other code in the CDL document needs to change.

Troubleshooting

  • If your test results do not match your expected results, create sampling probes in the Clock-Driven Logic document that you are testing. After the host VI executes, you can view the data that the sampling probes collect in the Sampling Probes tab and use the data to debug your code.
  • The complexity needed in the host VI varies depending upon the complexity of the CDL document you are testing. For example, if the CDL document uses handshaking or pipelining, you might need more complex code in the host VI to fully test the CDL document. If your test only uses code that is available on the FPGA, consider testing by simulating your CDL document in a Clock-Driven Loop on the diagram of an FPGA VI.

Examples

Search LabVIEW for the following installed example: Sampling Probes

Search LabVIEW for the following installed lesson: Programming with Clock-Driven Logic.


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