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Monitoring the Compilation of a Bitfile

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    Last Modified: April 26, 2016

    An FPGA target contains a limited number of resources. If a bitfile requires more resources than the FPGA target has available, the compilation of the bitfile fails. LabVIEW reports the estimated and actual number of resources used by a bitfile to help you determine changes you need to make to the code.

    Compilation can take a long time, so you can monitor the process and cancel a compilation if you encounter severe errors, instead of waiting for the entire process to finish.

    Complete the following steps to monitor the compilation of a bitfile.

    1. Double-click a bitfile row listed in the Compile Queue tab to monitor the status of your bitfile during compilation.
      spd-note-
      Warning  

      Do not change any code in your FPGA VI during the diagram analysis stage of compilation. Any changes you make to code during the diagram analysis stage may be reflected in the bitfile. If you want to continue working on code while you wait for the compilation to finish, do so after the diagram analysis stage.

    2. After the synthesizing stage of compilation, click each resource listed under Estimated Resource Usage to view the estimated FPGA resources that your bitfile requires. If LabVIEW estimates that your bitfile needs more resources than the FPGA target contains, you can cancel the compilation and revise your code. If you cancel a compilation, you must begin a new compilation to compile your updated code.
    3. Click the resources listed under Actual Resource Usage after the compilation finishes to see the total number of each resource used on the FPGA target. If your compilation fails, you can use the resource usage information to investigate errors or determine changes you need to make in your code. For example, if your bitfile uses all LUTs from the FPGA, but few block RAMs, you may need to change the way implement memory or FIFOs in your code.

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