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Execution of FPGA Code

Last Modified: April 22, 2016

You can run FPGA code on the FPGA directly or you can run the code on the host computer to simulate running it on the FPGA.

Execution on an FPGA

Code that executes on the FPGA target requires following a process to create and download a bitfile to the FPGA.

You compile a build associated with an FPGA VI to create a bitfile (.lvbitx). The bitfile contains binary data that describes how to configure the FPGA circuit so that it performs the same function as the code in the FPGA VI. You then download this bitfile to the FPGA, and when the application runs, the bitfile reconfigures the FPGA circuit of the FPGA target. Use the FPGA Host Interface nodes to download, run, and communicate with the FPGA VI on the FPGA.

Compiling the build can take a significant amount of time and varies depending on the size of the VI, the processor speed, and the amount of memory in the computer on which you are compiling.

Simulation on the Host Computer

FPGA code that executes on a host computer, in simulation, does not require compilation of the build and makes it easier and less time consuming to repeat tests until you're ready to compile and deploy to an FPGA.


You cannot run an FPGA VI in simulation on a real-time host.

You can run an FPGA VI in simulation on the host to test and debug the code. When you click the Run button from the panel or diagram of an FPGA VI, LabVIEW runs your code on the host computer rather than on the FPGA. Because the bitfile is not created and downloaded to the FPGA, you can test and debug the logic of your FPGA code more quickly. You also have access to debugging tools, such as breakpoints and probes, that you don't have access to when the code runs on an FPGA.

In addition to testing that the code in the FPGA VI works as you expect it to while you develop it, you also need to test how the FPGA code works in relation to the rest of your application. For example, you use a host VI to pass data to the FPGA VI to process. To make sure the host VI communicates as expected with the FPGA VI before you compile it, you can use the FPGA Host Interface nodes to run and communicate with the FPGA VI in simulation.

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