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Designating a Top-Level FPGA VI

Last Modified: January 11, 2018

Before compiling an FPGA application, designate a top-level FPGA VI that organizes all code you want to send to the FPGA.

  1. In SystemDesigner, select the VI on the FPGA that you want to designate as the top-level FPGA VI.
  2. In the Item tab, select Bitfile from the Build Output pull-down menu.
When you designate a bitfile build output for the FPGA VI, you define the VI as the top-level container for all other documents referenced by that VI.

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